This is Revision A of the Extensible Multiple Device Programmer 3 and it is currently a work in progress.
This is revision A of the EMDP3 mother board.
The parts list is kept in a separate file.
The power supply circuit diagram is shown below:
The power supply uses a Underwriters Labratory® approved "wall wart" to provide 24VDC of power. This means that the base board does not have any 110 AC or such voltages running around on it. The power comes in on either N1 (on board) or N3 (off board). The power switch can either be on board at SW1 or off board as SW2 through connector N2. A resettable polyswitch fuse is used to deal with short circuits at F1. D1 is a shorting diode that should trigger F1 if somehow a VAC power source gets plugged into N1 or N3.
The rest of the power supply a series of inexpensive linear voltage regulators, VR1-VR5, that step the voltage from 24 volts, to 18 volts, to 12 volts, to 8 volts and finally to 5 volts. All of these supplies are used elsewhere on the board except the 18 volt one, which is used to keep the 24 volt regulator, VR1, from disapating too much heat. The capacitors are tantalum for their low series resistance. This design will not win any energy conservation awards, but since the EMPD3 should spend 99% of its time turned off, there should be no real complaints. Finally, green LED D2 lights up to indicate that the device is turned on.
The serial communications circuit diagram is shown below:
The EMDP3 is a board that uses standard serial communcations protocols. Connector N6 is used connect to a DB9 port on a host computer that uses RS-232 voltage levels for signalling. U7 in conjunction with C7 through C10 converts the RS-232 levels to 5 volt levels. Connector N7 uses a RJ45 jack to provide RS-422 using SimpliciNet pin outs. The nifty DS8921AT at U10 provides RS-422 to 5 volt signalling level conversions.
U9A OR's the recevied signal from U7 or U10 and forwards the signal to the slave microcontroller (U1), the master microcontroller (U2), and to some gating circuitry that potentially gates the signal onto one of the bi-directional bus lines.
U9B OR's the transmit signals from the slave microcontroller (U1), the master microcontroller (U2), and through some gating logic with U8, potentially one of the bi-directional bus; the OR'd signal is forwarded to both the RS-422 connector and RS-232 connector.
The co-processor circuit diagram is shown below:
The co-processor is responsible for managing the EMDP3 base board. It consists of a PIC16F628, U1, ...
The low voltage processor circuit diagram is shown below:
U1 is low voltage processor is a low-voltage PIC16LF877. This microcontroller has direct access to all 30 of the bidirectional lines. The remaining two lines are LVPRX for serial data recieve, LVPTX for serial data transmit. The adaptor boards can be connected to the bus via the 37-pin female D connector N4.
Upon startup, the coprocessor is in charge. It immediately asserts LVPRESET# to force the low voltage processor into the reset state. Eventually, it will get around to setting VIO to the correct voltage and will release LVPRESET#. After that, the low voltage processor initializes itself and forces the bus lines to high impedance. Next, the programming algorithm is downloaded over the serial lines LPVRX and LVPTX.
The level shifting circuit diagram is shown below:
All level shifting from VCC (5 volts) to VDD (2 to 5 volts) is done by level shifting IC's U11 through U14. U11 and U12 are "up shifters" that take signals from VDD levels up to VCC levels and U13 and U14 are "down shifters" that take signals the opposite direction. The only c it will get around to setting VIO to the correct voltage and will release LVPRESET#. After that, the low voltage processor initializes itself and forces the bus lines to high impedance. Next, the programming algorithm is downloaded over the serial lines LPVRX and LVPTX.
The level shifting circuit diagram is shown below:
All level shifting from VCC (5 volts) to VDD (2 to 5 volts) is done by level shifting IC's U11 through U14. U11 and U12 are "up shifters" that take signals from VDD levels up to VCC levels and U13 and U14 are "down shifters" that take signals the opposite direction. The only chip that actually operates at VDD levels is U1, the slave microcontroller. Everything else is immediatehip that actually operates at VDD levels is U1, the slave microcontroller. Everything else is immediately shifted up into the VCC level domain where any supsequent manipulation occurs. The reason for this is because it is hard to find random logic chips that can tolerate a wide range in supply voltages. The PIC16LF877 can be run from 2 to 5.5 volts.
Bidirectional lines BD0 through BD7 are the 8 data lines set aside on the bi-directional bus. These are level shifted up U11 and U12 to VCC signaling levels that are fed into the U4 latch. BD8 is used as the SRDWR read and write select line. When SRDWR is asserted along with STB, the 8 data values are written into the U4 latch. When SRDWR is low and STB is asserted, the two wonderful bits of data are read back from the master processor via BD0 and BD1. The random logic does this is shown in another diagram. The TX pin of U1 is STX and gets level shifted up to MSTX with VCC signal levels. Lastly, BD22 is connected to a bi-directional line and is level shifted up to BTX, which with approval from the master microcontroller gets OR'd into the serial transmit stream.
There is one buttons, SW2 that can be read by the coprocessor. SW2 is used to initiate programming from the programmer.
Lastly, the STB signal is on RA5 of microcontroller U1. This pin has an open collector output an needs to be pulled high by R21. The data coming back from the IDDAT line is pulled high by R22 to detect when there is now adaptor/plug connected to the system.
The Digital to Analog converters circuit diagram is shown below:
The digital to analog converter is implemented by U15, a serial quad 8-bit D/A. All of the reference voltages are tied to 2.5 volts. D/A output A is used to generate VAR1, a 0 to 24 output in .1 volt increments. D/A output B is used to generate a 0 to 10 volt output in .05 volt increments. D/A output C is used to genarate a 0 to 8 volt output in increments of .05 volts.
All three amplifiers are the same basic design with different resistor values to change the over gain. A transistor is in the feedback circuit to provide additional current capacity.
The clock management circuit diagram is shown below:
This is a place holder until I get around to redesigning the clock generator.
Alas, none of the PCB work has even been started.
The following printed circuit board files are available:
Any fabrication issues will be listed here.
