This is an EMDP1 Adaptor and it is currently a work in progress.

EMDP1 AVR Adaptor Board

The following revisions of the AVR EMDP1 Adaptor board are listed below:

Revision A
The first revision of the AVR adaptor board.

Research

Atmel® has come up the following different ways of programming their AVR chips:

Parallel Programming
The chip is programmed 8 bits at a time via a parallel interface. This mode is typically entered by putting RESET* to 12 volts.
SPI Serial Programming
The chip is programmed using the an SPI serial bus interface. This mode is typically entered by holding RESET* at ground.
AVR Serial Programming
The chip is programmed using a AVR specific programming standard. This is typically only used on the 8-pin parts and is entered by applying 12 volts to RESET*.
JTAG Programming
The JTAG standard is used to program the AVR chip.
Boot Loader
A preloaded boot loader is used to program the AVR chip.
This adaptor started out as an exploration of supporting all of the programming methods. Eventually, it got reduced to just the SPI Serial Programming method and the AVR Serial Programming method.

The various methods are summarized in the table below:

Processor Parallel Prog. SPI Serial Prog. AVR Serial Prog. JTag Prog. Boot Loader
AT90S1200 X (12V) X (0V) - - -
AT90S2313 X (12V) X (0V) - - -
AT90S/LS2323 - X (0V) X (12V) - -
AT90S/LS2343 - X (0V) X (12V) - -
AT90S/LS4433 X (12V) X (0V) - - -
AT90S/LS8535 X (12V) X (0V) - - -
AT90S/LS8515 X (12V) X (0V) - - -
ATmega8 X (12V) X (0V) - - X
ATmega16 X (12V) X (0V) - X X
ATmega32 X (12V) X (0V) - X X
ATmega64 X (12V) X (0V) - X X
ATmega103 X (12V) X (0V) - - -
ATmega128 X (12V) X (0V) - X X
ATmega161 X (12V) X (0V) - - X
ATmega162 X (12V) X (0V) - X X
ATmega163 X (12V) X (0V) - - -
ATmega323 X (12V) X (0V) - X X
ATmega8515 X (12V) X (0V) - - X
ATmega8535 X (12V) X (0V) - - X
ATtiny11 - - X (12V) - -
ATtiny12 - X (0V) X (12V) - -
ATtiny15 - X (0V) X (12V) - -
ATtiny26 X (12V) X (0V) - - -
ATtiny28 X (12V) - - - -
As a quick summary, it is interesting to note that all chips except the ATtiny28 can be programmed using either the SPI or AVR serial programming method.

The next part of the task is to determine which pins are used for each mode and map them to a 40-pin zero insertion force socket.

Parallel Programming

Proc. Pkg RDY/BSY* OE* WR* BS XA0 XA1 Clock BS2 PAGEL Data RESET* VCC GND
AT90S1200 DIP20 PD1 3 PD2 6 PD3 7 PD4 8 PD5 9 PD6 11 XTAL1 5 PB0-7 12-19 (12V) 1 (5V) 20 10
AT90S2313 DIP20 PD1 3 PD2 6 PD3 7 PD4 8 PD5 9 PD6 11 XTAL1 5 PB0-7 12-19 (12V) 1 (4.5-5.5V) 20 11
AT90S4433 DIP28 PD1 3 PD2 4 PD3 5 PD4 6 PD5 11 PD6 12 XTAL1 9 (12V) 1 PC1-0, PB5-PB0 14-19, 23-24 (4.5-5.5V) 7 8
AT90S8535 DIP40 PD1 15 PD2 16 PD3 17 PD4 18 PD5 19 PD6 20 XTAL1 13 PB7-PB0 1-8 (12V) 9 (4.5-5.5V) 10 11
AT90S/LS8515 DIP40 PD1 11 PD2 12 PD3 13 PD4 14 PD5 15 PD6 16 XTAL1 18 PB7-PB0 1-8 (12V) 9 (4.5-5.5V) 40 20
ATmega162 DIP40 RDY/BSY* OE* WR* BS XA0 XA1 BS2 Pagel Clock Data RESET* VCC GND
ATmega163 DIP40 PD1 11 PD2 12 PD3 13 PD4 14 PD5 15 PD6 16 XTAL1 19 PA0 39 PD7 17 PB7-PB0 1-8 (12V) 9 (5V) 40 (0V) 20
ATtiny28 DIP28 PD1 3 PD2 4 PD3 5 PD4 6 PD5 11 PD6 12 XTAL1 9 PB7-PB0 24[36],23[35],19[31]-15[27], 14 1 7, 20[32] 8, 22[34]
ATtiny28 Summary DIP40 3, 4, 5, 6, 9, 11, 12, 14, 27, 28, 29, 30, 31, 35, 36 1, 7, 8, 32, 34
I got tired reading the parallel programming specifications. It clearly uses way more pins than the serial methods below. It seems quite likely that the only parallel method that needs real investigation is the parallel method needed for the ATtiny28. So I skipped over to that one and entered it into the table. The rest of rows in the table are ignored.

SPI Serial Programming (Done)

Processor Package SCK MISO MOSI Clock Reset* VCC Ground Plug Id
AT90S1200. DIP20 PB7 19 [39] PB6 18 [38] PB5 17 [37] XTAL1 5 1 (2.7-6.0V) 20 [40] 10 3
AT90S2313. DIP20 PB7 19 [39] PB6 18 [38] PB5 17 [37] XTAL1 5 1 (2.7-6.0V) 20 [40] 10 3
AT90S/LS2323. DIP8 PB2 7 [39] PB1 6 [38] PB0 5 [37] XTAL1 (8MHz) 2 1 (2.6-6.0V) 8 [40] 4 0
AT90S/LS2343. DIP8 PB2 7 [39] PB1 6 [38] PB0 5 [37] PB3 (8MHz) 2 1 (2.6-6.0V) 8 [40] 4 0
AT90S/LS4433. DIP28 PB5 19[31] PB4 18[30] PB3 17[29] XTAL1 9 1 (2.7-4.0-6.0V) 7, 20 [32] 8, 22 [34] 4
AT90S/LS8535 DIP40 PB7 8 PB6 7 PB5 6 XTAL1 13 9 (2.7-6.0V) 10 11 2
AT90S/LS8515 DIP40 PB7 8 PB6 7 PB5 6 XTAL1 19 9 (2.7-6.0V) 40 20 1
ATmega8 DIP28 PB5 19 [31] PB4 18 [30] PB3 17 [29] XTAL1 9 1 (2.7-5.5V)7, AVCC 20 [32] 8 22 [34] 4
ATmega16 DIP40 PB7 8 PB6 7 PB5 6 XTAL1 13 9 (2.7-5.5V)10, AVCC (2.7-5.5) 30 11, 31 2
ATmega32 DIP40 PB7 8 PB6 7 PB5 6 XTAL1 13 9 (2.7-5.5V) 10, AVCC (2.7-5.5) 30 11, 31 2
ATmega64 TQFP64 PB1 11 PE1 3 PE0 2 XTAL1 24 20 21, 52, AVCC 64 22, 53, 63
ATmega103 TQFP64 PB1 11 PE1 3 PE0 2 XTAL1 24 28 21, 52 22, 53
ATmega128 TQFP64 PB1 11 PE1 3 PE0 2 XTAL1 24 20 (2.7-5.5) 21, 52, AVCC (2.7-5.5) 64 22, 53, 63
ATmega161 DIP40 PB7 8 PB6 7 PB5 6 19 9 40 20 1
ATmega162 DIP40 PB7 8 PB6 7 PB5 6 XTAL1 19 9 40 20 1
ATmega163 DIP40 PB7 8 PB6 7 PB5 6 XTAL1 19 9 (5V?) 40 (0V) 20 1
ATmega323 DIP40 PB7 8 PB6 7 PB5 5 XTAL1? 13 9 (2.7-5.5) 10, AVCC 30 11, AGND 31 2
ATmega8515 DIP40 PB7 8 PB6 7 PB5 6 19 9 40 20 1
ATmega8535 DIP40 PB7 8 PB6 7 PB5 6 XTAL1 13 9 (2.7-5.5) 10, AVCC (2.7-5.5) 30 11, 31 2
ATtiny12 DIP8 PB2 7[39] PB1 6[38] PB0 5[37] XTAL1/PB3 2? PB5 1 (2.2-5.5V) 8[40] 4 0
ATtiny15 DIP8 PB2 7[39] PB1 6[38] PB0 5[37] - PB5 1 (2.7-5.5V) 8[40] 4 0
ATtiny26 DIP20 PB2 3 PB1 2 PB0 1 PB4 7 PB7 10 (2.7-5.5V) 5, AVCC 15[35] 6, AGND 16[36]? 5
Summary DIP40 3, 8, 31, 39 2, 7, 30, 38 1, 6, 29, 37 2, 7, 9, 13, 19 1, 9, 10 5, 7, 10, 30, 32, 35,40 4, 6, 8, 11, 20, 31, 34, 36
Summary - DIP8 DIP40 3, 8, 31 2, 7, 30 1, 6, 29 7, 9, 13, 19 1, 9, 10 5, 7, 10, 30, 32, 35,40 6, 8, 11, 20, 31, 34, 36
Summary - DIP8 DIP40 1, 2, 3, 6, 7, 8, 9, 13, 19, 29, 30, 31 1, 5, 6, 7, 8, 9, 10, 11, 20, 31, 30, 32, 34, 35, 36, 40
The SPI serial method sure is pin intense when summarized over all chips, but it still appears workable.

AVR Serial Programming (Done)

Processor Package Ser. Data Out Ser. Instr. In Ser. Data In Clock Reset* (VPP) VCC Ground Plug Id
AT90S/LS2323 DIP8 PB2 7[39] PB1 6[38] PB0 5[37] XTAL1 2 (11.5-12.5V) 1 (4.5-5.5V) 8[40] 4 0
AT90S/LS2343 DIP8 PB2 7[39] PB1 6[38] PB0 5[37] PB3 2 (11.5-12.5V) 1 (4.5-5.5V) 8[40] 4 0
ATtiny11/12 DIP8 PB2 7[39] PB1 6[38] PB0 5[37] PB3/XTAL1 2 (11.5-12.5V) 1 (4.5-5.5V) 8[40] 4 0
ATtiny15 DIP8 PB2 7[39] PB1 6[38] PB0 5[37] - (11.5-12.5V) 1 (4.5-5.5V) 8[40] 4 0
Summary DIP40 39 38 37 2 1 40 4
Summary DIP40 2, 37, 38, 39 1, 4, 40
This is nice, all AVR serial programmable chips use the same exact pins. Nice.

JTAG Programming (Done)

Processor Package TCK TMS TDO TDI VCC Ground
ATmega16 DIP40 PC2 24 PC3 25 PC4 26 PC5 27 10 11, 31
ATmega32 DIP40 PC2 24 PC3 25 PC4 26 PC5 27 10 11, 31
ATmega64 TQFP64 PF4 57 PF5 56 PF6 55 PF7 54 21, 52 22, 53
ATmega128 TQFP64 PF4 57 PF5 56 PF6 55 PF7 54 21, 52 22, 53
ATmega162 DIP40 PC4 25 PC5 26 PC6 27 PC7 28 40 20
ATmega323 DIP40 PC2 24 PC3 25 PC4 26 PC5 27 10 11
Summary DIP40 24, 25 25, 26 26, 27 27, 28 10, 40 11, 20, 31
Summary DIP40 24, 25, 26, 27, 28 10, 11, 20, 31, 40
The JTAG programmable parts need pins 24-28 above and beyond what the serial programmable chips need.

The table below attempts to figure out what pins need to be able to have VAR1, VAR2, and Ground routed to them.

Method Reset* Vcc Ground Overlapping Other Unique Other
JTAG 10, 11, 20, 31, 40 24, 25, 26, 27, 28 24, 25, 26, 27, 28
Parallel 1, 7, 8, 32, 34 3, 4, 5, 6, 9, 11, 12, 14, 27, 28, 29, 30, 31, 35, 36 3, 4, 5, 6, 9, 11, 12, 14, 27, 28, 29, 30, 31, 35, 36
SPI Serial
(no DIP8)
1, 5, 6, 7, 8, 9, 10, 11, 20, 31, 30, 32, 34, 35, 36, 40 1, 2, 3, 6, 7, 8, 9, 13, 19, 29, 30, 31 2, 3, 13, 19, 29
AVR Serial 1, 4, 40 2, 37, 38, 39 2, 37, 38, 39
SPI & AVR Serial 1, 4, 5, 6, 7, 8, 9, 10, 11, 20, 30, 31, 32, 34, 35, 36, 40 1, 2, 3, 6, 7, 8, 9, 13, 19, 29, 30, 31, 37, 38, 39 2, 3, 13, 19, 29, 37, 38, 39
SPI & AVR Serial & Parallel 1, 4, 5, 6, 7, 8, 9, 10, 11, 20, 30, 31, 32, 34, 35, 36, 40 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 19, 27, 28, 29, 30, 31, 35, 36, 37, 38, 39 2, 3, (12), 13, (14), 19, (27), (28), 29, 37, 38, 39
An adaptor that attempts to support all formats requires a lot of pins. Every chip that can be programmed by JTAG can also be programmed by some other technique, so JTAG is dropped. This allows us to avoid running wires to pins 24-26. The ATtinyt28, is the only chip that requires parallel only. All of the 8-pin chips can be programmed via AVR serial, so we drop DIP8 programming from the SPI serial pins. Adding the ATtiny28, requires 4 additional wires to pins 12, 14, 27, and 28, but that is acceptable, since we have the available BD wires.

The various plugs are roughed out below:

Plug Id Name Connections
0 AVR8 RESET*:1-VAR1; Ser. Data Out:ZIF39-BD?; Ser. Data In: ZIF38-BD?; CLK: ZIF2-BD?; GND: ZIF4-GND; VCC: ZIF40-VAR2
1 AVR40 RESET*:ZIF9-VAR1; SCK:ZIF8-BD?; MISO:ZIF7-BD?; MOSI:ZIF6-BD?; CLK:ZIF19-BD?; GND:ZIF20-GND; VCC:ZIF40-VAR2
2 AVR41 RESET*:ZIF9-VAR1; SCK:ZIF8-BD?; MISO:ZIF7-BD?; MOSI:ZIF6-BD?; CLK:ZIF13-BD?; GND:ZIF11-ZIF31-GND; VCC:ZIF10-ZIF31-VAR2
3 AVR20 RESET*:ZIF1-VAR1; SCK:ZIF19-BD?; MISO:ZIF18-BD?; MOSI:ZIF17-BD?; CLK:ZIF5-BD?; GND:ZIF10-GND; VCC:ZIF40-VCC
4 AVR28 RESET*:ZIF1-VAR1; SCK:ZIF19-BD?; MISO:ZIF18-BD?; MOSI:ZIF17-BD?; CLK:ZIF9-BD:?; GND:ZIF8-ZIF34-GND; VCC:ZIF7-ZIF32-VAR2;
5 AVR26 RESET*:ZIF10-VAR1; SCK:ZIF3-BD?; MISO:ZIF2-BD?; MOSI:ZIF1-BD?; CLK:ZIF7-BD:?; GND:ZIF6-ZIF36-GND; VCC:ZIF5-ZIF35-VAR2;
6 AVR29 RESET*:ZIF1-VAR1; OE*:ZIF4-BD?; WR*:ZIF5-BD?; BS:ZIF6-BD?; XA0:ZIF11-BD?; CLK:ZIF9-BD?; D4:ZIF30-BD?; D5:ZIF31-BD?; D6:ZIF35-BD?; D7:ZIF36-BD?; VCC:ZIF7-ZIF32-VAR2; GND:ZIF8-ZIF22-GND
The ATtiny28 uses plug 6.

The plug is sumarized as follows:

Usage Count
Plug to ZIF 17
BD to Plug 9
Plug ID 4
Ground VAR1 VAR2 3
Total 33
A 34-pin female plug is available from Jameco (part number 163862), so the plug will be 2×17 (=34) pins. One more pin is added to run ZIF pin 19 to the plug (see below), so all 34 pins will be used.

The table below summarizes BD line usage:

Usage Count
BD to ZIF 12
BD to Plug 9
ROM Type 2
Program LED 1
Plug ID 4
Total 28
This is one more than the 27 BD lines that are available. With the exception of the ATtiny28, all of the other personality plugs can survive with only 4 BD lines running to the plug. The ATtine28 needs 5 extra BD lines running to the plug. We work around this problem by running ZIF pin 19 onto the personality plug as well. Pin 19 is only used by plug 1, so there are plenty of BD lines left over on the plug. This frees up one BD line and gets us to 27 BD lines. (Whew, that was close.)


Copyright (c) 2002 by Wayne C. Gramlich. All rights reserved.