This is the EMDP3 bus specification for the EMDP3 system and it is currently a work in progress.

EMDP3 Bus

Table of Contents

• 1.0 Introduction
• 2.0 Bus Overview
• 3.0 Bidirectional Lines
  • 3.1 Overloaded_Parallel Bus
  • 3.2 Overloaded Serial Bus
  • 3.3 Overloaded Serial Communication
  • 3.4 Overloaded Interrupt
  • 3.5 Overloaded JTAG
  • 3.6 Overloaded Selectable Clock
• 4.0 Identification
• 5.0 Power and Ground
• 6.0 Bus Connectors
• 7.0 Bus Rationale

1.0 Introduction

The EMDP3 bus is a 37 wire bus. Some of the wires are allocated for power distribution, some are used for adaptor and rewiring plug identifaction and the remaining wires are used for general purpose device programming.

2.0 Bus Overview

Table below summarizes what each pin of the EMDP3 is used for.

CUMP Bus (Rev.4)
DB37 Pin #	IDC Pin #	Signal Name		IDC Pin #	DB37 Pin #
1	1	TX/BD0	BD1/RX	2	20
2	3	BD2	BD3	4	21
3	5	BD4	BD5	6	22
4	7	BD6	BD7	8	23
5	9	ICP/BD8	BD9/OCP	10	24
6	11	PP0/BD10	BD11/PP1	12	25
7	13	PP2/BD12	BD13/PP3	14	26
8	15	PP4/BD14	BD15/PP5	16	27
9	17	PP6/BD16	BD17/PP7	18	28
10	19	PCK#/BD18	BD19/RW#	20	29
11	21	ALE#/BD20	BD21/DBR	22	30
12	23	IRQ#/BD22	BD23/SDI	24	31
13	25	GND	BD24/SDO	26	32
14	27	5V	BD25/SCK	28	33
15	29	VIO	BD26/SCL	30	34
16	31	VAR2	BD27/SDA	32	35
17	33	VAR1	BD28/VCK	34	36
18	35	IDD	BD29/IDL	36	37
19	37	IDC	NC	38	n/a
n/a	39	NC	NC	40	n/a

Abrev.	Description
VAR	Variable Voltage
VCC	Supply voltage (5V/3V?)
GND	0V
BD	BiDirectional signal
PP	Parallel Port signal
E	Parallel Port Enable (aka parallel port clock)
RW	Parallel Port Read/Write signal
ALE	Parallel Port Address Latch Enable
SDA	IIC Serial Data
SCL	IIC Serial Clock
SDI	SPI Serial Data In
SCK	SPI Serial Clock
SDO	SPI Serial Data Out
VCLK	Variable Clock source
TX	UART data send (MB centric)
RX	UART data receive (MB centric)
IDC	Serial ID clock
IDD	Serial ID data
IDL	Serial ID load
IRQ	Interrupt Request
NC	Not Connected

The material below is OUT OF DATE!!!

3.0 Bidirectional Lines

There are 30 EMDP3 bus lines that are set asside for general purpose device programming:

BD1-BD30 (BiDirectional 1 - BiDirectional 30)

General purpose bidirectional lines.

Some of the bidirectional lines have overloaded functions that can be assigned to them. These alternate functions are listed below:

Parallel Bus

The parallel bus is an 8-bit bus that is used to 8-bit latches and buffers.

Serial Bus (I²C and SPI)

Some devices use the popular I²C and SPI buses for device programming. Since some EMDP3 bases have hardware support for these two protocols, they have been assigned to two specific pins on the EMDP3 bus. If a given EMDP3 base microcontroller does not have hardware support for either of the two protocols, it can "bit bang" the protocols instead.

Selectiable Clock

Some devices need a clock signal to get the internal circuitry prepared for programming. The selectable clock pin can be programmed to generate up to 8 different clock rates up to 1 MHz.

Serial Communication (RX and TX)

It is concievable that some adpators will choose to have on board microcontrollers to do specific device dependent operations. The on board microcontroller chip can communicate with the host software via the the RX and TX pins on the EMDP3 bus.

3.1 Overloaded Parallel Bus

14 bi-directional lines and one other line (STB) are used to implement the overloaded parallel bus. The overloaded parallel bus serves two purposes:

• it provides a means for the controlling microcrontroller to access 8-bit located ports on the base board.
• it provides a means for the controlling microcontroller to access 8-bit ports located on rewiring plugs.

The overloaded parallel bus consists of the following lines:

Number	Name
8	D0, ..., D7
4	A0, ..., A3
1	RD
1	WR
1	STB

3.1.1 Accessing Base Ports

The EMDP3 base can have up to 16 ports on its printed circuit board. These ports use D0:7 for data and A0:3 for addressing. The RD and WR lines are not used. To read an on-board port, the microcontroller sets D0:7 to be inputs, outputs the correct address values on A0:3, asserts STB, and reads the value off of D0:7. To write to an on-board port, the microcontroller set D0:7 to contain the data value, A0:3 to have the correct address, and asserts STB. The address implicitly specifies whether STB is a read or a write operation. The RD and WR lines remain unchanged.

The overloaded parallel bus allows the use of a microcontroller that has only 33 I/O lines (e.g. PIC16F877.) This is done by using 30 of the lines for bi-directional bus lines, assigning the UART TX and RX lines for communication with the host computer, and using the remaining line for STB. All other base functions (e.g. busy LED, clock select, etc.) can be done using ports laying off of the overloaded parallel bus.

Whenever the microcontroller needs to access its internal ports, the programming algorithm needs to allow the microcontroller to temporarily `borrow' the bi-directional lines needed for the overloaded parallel bus. This accomplished by having the person that designs the rewiring plug for the algorthm use the overloaded lines primarily for output data and address lines (not control lines.) For example, the 27C080 is a 1MB × 8 EPROM that has 20 address lines and 8 data lines. The plug designer for this chip would probably assign the overloaded parallel bus to the 20 address lines of the 27C080.

Note that whether STROBE is active high or low is not important; it is design decision that EMDP3 base designer makes.

3.1.2 Accessing Plug Ports

The EMDP3 base can access up to 16 ports on the rewiring plug. This transaction requires D0:7, A0:3, RD and WR. STB is not used. To write 8-bits of data, the data is placed on D0:7, a port address is placed on A0:3, and WR is asserted. To read 8 bits of data, the D0:7 is turn into inputs, a port address is placed on A0:3, and RD is asserted. At no point is ever STB asserted.

The RD and WR signals can be either active high or low; this decision is left up to the person who designs the rewiring plug.

3.2 Overloaded Serial Bus

Most higher end microcontrollers have some sort of hardware support for I²C^® and/or SPI^®. The I²C bus requires two open collector lines SCL and SDA. The SPI bus requires SDO, SDI, and SCK. These lines are mapped so that SCL and SCK are on the same bi-directional line, SDI and SDA are one the same bi-directional line and SDO is on its own bi-directional line.

If the microcontroller does not implement SPI, it can be done via bit-banging (technical term) in software. Likewise, if the microcontroller does not implement I²C, it can be bit banged as well. If the microcontroller implements both SPI and I²C and, the base board designer is responsible for making sure that SCL and SCK are on the same bi-directional line as well as SDI and SDA on another. If the hardware does not support this, the base designer can still opt to implement one in software (probably SPI because it is easier) and the other in hardware. Alternatively, the designer may come up with some clever signal routing hardware that ensures that the right signals are on the right pins. A small DPDT relay is both inexpensive and up to the task. Lastly, the plug designer is responsible for providing the requisite pull up resistors.

3.3 Overloaded Serial Communication

Sometimes adding a few extra 8-bit ports to the wiring plug is not enough, and even more hardware support is required. For this hopefully rare situation, an entire microcontroller can be placed directly on the rewiring plug. This microcontroller is called the plug microcontroller to distinguish it from the base microcontroller.

The RX and TX signals of the plug microcontroller can be connected to the appropriate overloaded bi-directional lines. The base controller arranges so that transmitted bytes via the TX are sent up to the host computer. Received bytes are returned via the RX line are received by the plug microcontroller.

3.4 Overloaded Interrupt

Sometimes there is a condition on the rewiring plug that needs immediate attention. The INT line can be asserted to force the base microcontroller to experience an interrupt.

3.5 Overloaded JTAG

{We really need JTAG support. I do not know squat about JTAG support.}

3.6 Overloaded_Selectable Clock

Some devices require a clock signal to be present on one of the device pins before programming can proceed. The availble clock rates are:

Selector	Frequency
0	16 MHz
1	8 MHz
2	4 MHz
3	2 MHz
4	1 MHz
5	.5 MHz
6	.25 MHz
7	.125 MHz

4.0 Identification

5.0 Power and Ground

6.0 Bus Connectors

7.0 Bus Rationale